ASICs and Programmable Logic Devices (PLDs) represent two distinct types of Integrated Circuits (ICs) that perform specific logic operations. ASICs are distinguished from PLDs in that ASICs are customized during the design and fabrication process to implement a user's logic function, while PLDs are provided with programmable circuitry that is configured (programmed) by a user after the PLD is fabricated.
FIG. 1 is a flow diagram illustrating a simplified conventional process for designing and fabricating an ASIC 100. At the beginning of the design phase, a circuit designer typically selects an ASIC family that is defined, for example, by the feature and chip size of the completed ASIC, along with any pre-defined arrangements of transistors and/or contact pads. The user then enters a logic design into a computer or workstation 110 using an input device 111. Computer 110 is loaded with a logic design entry software tool 113 that is typically linked to a design library 115 containing design parameters associated with the selected ASIC family. Design library 115 also typically includes one or more pre-defined logic elements (often referred to as “macros”) that can be selected by the user during the logic design entry process. The user utilizes entry tool 113 to link these pre-defined logic elements with custom-designed logic elements (if any) to construct the logic design. Once the logic design is entered, place and route tools 117, also loaded on computer 110, are utilized to generate a place-and-route solution, which arranges the various interrelated portions of the logic design in an efficient two-dimensional spatial relationship that can be fabricated on a chip, and generates signal (interconnect) lines for passing signals between the interrelated portions. A layout tool 119 is then utilized to construct a three-dimensional representation of the actual circuit structures (e.g., regions of doped semiconductor, insulated regions, and metal lines) needed to implement the logic design. Next, this three-dimensional representation is then used to generate a set of masks (step 120) that are then used to fabricate ASIC 100 (step 130) using known techniques.
Two popular techniques for building ASICs are Mask-Programmed Gate Arrays (MPGAs), Standard Cell or Cell Based Integrated Circuits (CBICs).
FIG. 2 is a perspective view showing a simplified MPGA 200, along with a mask set 210 used during the fabrication phase used to form MPGA 200. MPGA 200 includes rows of pre-defined transistors 202 and surrounding bonding pads 205 that are laid-out independent of the design to be manufactured. Specifically, mask set 210 includes a first group of pre-defined masks 212 that are utilized during the fabrication of all ASICs “built” on MPGA 200. Note that during the ASIC design phase (described above), the placement process assigns portions of the logic function to selected pre-defined transistors 202. An ASIC is “built” on pre-defined transistors 202 using custom mask set 214 that produces interconnect wiring 206 between the assigned transistors 202 to perform the logic functions of the ASIC logic design. Because the layout of transistors 202 is the same for all designs, mask set 212 (i.e., the masks used to fabricate transistors 202) can be shared among all ASIC designs of a particular MPGA family, thereby reducing the costs and shortening the time needed to implement ASIC logic designs by reducing the number of custom masks. Further, the production of custom masks is facilitated using wiring patterns stored in design library 115 (see FIG. 1) that are provided for producing often-used circuit structures, such as logic gates. Typically, design library 115 provides lower level metal layer patterns that wire together predefined sets of transistors to build logic gates. The logic gates are interconnected by longer wires 206 using upper level metal layers to build the ASIC logic design. These upper level metal layers are defined by place and route tools 117. The use of such a design library further reduces the costs and shortens the time needed to implement ASIC designs by automating much of the custom mask design process.
In contrast to MPGAS, CBICs are essentially blank silicon substrates upon which both transistors and wiring connections are custom-made for each design. Similar to MPGAS, certain commonly-used structures (e.g., the transistors and wiring connections of logic gates) are selected from a design “library”, and are selectively arranged in custom cells according to a desired ASIC logic design. Because even the transistors are customized in CBICs, designs can be much more complex, and include dense memory and custom data path structures, at the cost of more mask-making and the need to develop custom cells for the logic gates.
Modern IC processes have reduced the size of transistors such that hundreds of millions of transistors to be inexpensively fabricated on a single MPGA or CBIC chip. However, as the numbers of transistors on each chip increase, noise in the interconnect wiring connecting these transistors is becoming an increasing problem. In particular, as IC manufacturing processes improve, signal delay, particularly for “long distance” signals (i.e., signals transmitted between distinct groups of transistors), is dominated by the signal delay caused by transmission through the interconnect wiring. Further, as interconnect wiring gets narrower and thinner with advanced processes, its resistance increases, thereby further delaying the transmission of signals over longer interconnect wires.
One method to address signal delays in long interconnect wires is to segment each interconnect wire into collinear wire segments that are connected in series by buffers. That is, an interconnect wire that spans a long distance in an ASIC design may produce a greater signal delay than a buffered series of wire segments that are optimized to reduce signal delays. The optimal wire segment length (i.e., spacing between buffers) of these buffered signal paths depends primarily on the process technology (i.e., the resistance and capacitance the wire). As process technology advances, the correct fixed length gets smaller and smaller. Further, the sizing of the wire segment and the positions of the buffers depend on nearby wire segments. Therefore, the optimal wire segment and associated buffer size will be different for each family of ASICs that are defined by these features.
A problem with incorporating buffered interconnect wires into a conventional ASIC design processes is the difficult task of automatically breaking the longer wires into optimal-length wire segments, and providing necessary silicon space for the buffers. According to conventional ASIC design processes, the tasks of designing the segmented interconnect wires and placing buffer structures are performed by conventional placement and routing tools, mentioned above, which are highly-sophisticated software programs. Modification of these software programs to break all wires into optimal-length wire segments and to provide buffer space is impractical because the calculations are too difficult to perform quickly during placement and routing. Further, routing must be done after placement, but buffer insertion requires that they be placed, so if buffers are inserted during routing, the placement must change, potentially requiring the route to be re-done also. As a result, it is difficult to predict the actual delay of signals transmitted between circuit groups in an ASIC design prior to routing. This prediction is needed in placement and synthesis to meet timing requirements for the ASIC design.
What is needed is a method and structure that facilitates predictable and optimal-speed interconnect wiring for long distance signal transmissions in ASIC designs. Preferably this method and structure would permit sharing of masks to reduce costs, yet allow custom transistors for dense memory blocks.